The present invention relates to the field of processor interface circuitry. More specifically, in one embodiment the invention provides an improved interface between a microprocessor, or a set of microprocessors, and other processor circuits.
In many cases, a microprocessor can be designed to run faster than external components with which it communicates. Unfortunately, the microprocessor often cannot proceed until a particular action is taken by the external device, and thus the performance of the processor system in which the microprocessor is used is adversely affected. One reason for this bottleneck is that communication between two circuits on the same integrated circuit, or chip, is generally faster than communication between two circuits separated by an inter-chip bus or other interface. Thus, one solution to the need for faster interaction with the microprocessor is to place more circuitry on the microprocessor chip, such as data and instruction caches. However, adding higher-level components on chip with the microprocessor make diagnosing errors much more difficult. This is because by the time an internal error is detected within the microprocessor and percolates out of the chip to a diagnostic system, the diagnostic system has much less time to investigate the cause of the error before the continued operation of the microprocessor changes the state of its internal circuits to the point where the state at the time of the error is no longer known. For example, if a data error occurs deep inside the microprocessor, but is detected and apparently fixed by logic inside the microprocessor before being output, external circuits may act on that data as being valid data thereby corrupting the processor system.
Another problem with processor systems is the microprocessor bus, over which most of the microprocessor requests and responses to those requests pass. The microprocessor bus carries write requests, along with the data to be written, read requests, read and write responses back to the microprocessor, and interrupt signals into the microprocessor. This traffic over the bus often limits the speed at which data can be accepted from, and provided to, the microprocessor.
From the above it is seen that an improved interface to a microprocessor is needed.